The Gem5 simulator is used in this study to assess the performance of a RISC-V architecture-based CPU. The Gem5 simulator is used to analyze performance measures such as bandwidth, latency, throughput, branch prediction, pipeline stages, and memory hierarchy in the processor architecture. Various simulation models are utilized to discover the optimal reference model for RISC-V architecture design and development. This reference model's cache memory functionality is verified using the Universal Verification Methodology verification methodology (UVM) Simulations reveal that the program and data cache have the best performance in terms of execution time, hit rates, miss rates, and miss latencies. The Gem5 simulator was used to evaluate the performance of several setups in order to discover the best one.
Author (s) Details
Lakshmaiah Alluri
HDG, CDAC, Thiruvananthapuram, India.
Dr. M. Bhaskar
Department of Electronics and Communication, NIT, Trichy, India.
Hemant Jeeven Magadam
ITNS, CDAC, Thiruvananthapuram, India
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