Recent Analysis of NAND Gate Based Phase Frequency Detector for Phase Locked Loop (PLL) | Chapter 7 | Research and Developments in Engineering Research Vol. 1

 Phase Locked Loop (PLL) must run at higher repetitions as RF IC technology advances, but low capacity consumption is more necessary. PLL is an indispensable component of electronic manufacturing. Proposed Phase frequency detector (PFD) design engaging a NAND gate that consumes considerably less power while too taking into account different limits such as rise period and slew rate over temperature alternatives. At 65∘c, the slew rate changes from 44 to 30 v/ns, and the rise time varies from 23 to 56 ps.

Author(s) Details:

Leela Bitla,
IT Department, G. H Raisoni College of Engineering, Nagpur, India.

V. Saraswathi,
ECE Department, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, India.

Rupali Vairagade,
IT Department, G. H Raisoni College of Engineering, Nagpur, India.

Please see the link here: https://stm.bookpi.org/RADER-V1/article/view/10093