Phase Frequency Detector (PFD) Design with Frequency Dividers for a Phase Locked Loop (PLL) in 0.18-μm CMOS Technology | Chapter 3 | Technological Innovation in Engineering Research Vol. 3

A novel CMOS dynamic Phase Frequency Detector design is presented in this paper (PFD). The proposed PFD circuit (PPFD) was created, simulated, and the results were evaluated. The PPFD circuit uses internal signal routing to eliminate dead zone. The Low Pass Filter (LPF) integrates error current to provide VCO control voltage and suppresses noise and undesirable phase detector outputs, which is what a Loop-filter is. The PLL is built in 0.18 m CMOS technology with a T-spice environment and coupled to the frequency divider circuits (FD/2 & FD 2/3). According to the comparisons, the low power consumption by the PLL with FD2/3 is around 0.65 W. In addition, the PLL circuits are subjected to Monte Carlo simulation, and the power values are examined. Pass transistor logic based FDs can be utilised to extend the research work and minimise power.

Author(s) Details:

N. K. Anushkannan,
Department of Electronics and Communication Engineering, Kathir College of Engineering, Coimbatore, India.

H. Mangalam,
Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore, India.

Please see the link here: https://stm.bookpi.org/TIER-V3/article/view/7058