The Mixed Logic Style based High-performance Binary Adder for ASIC Applications | Chapter 2 | Technological Innovation in Engineering Research Vol. 7

 Binary adders serve as the essential building blocks for developing data processing arithmetic units. In this paper, a novel one-bit complete adder developed using mixed logic design is presented (MLS). Several logic topologies, including High-Skew (Hi-Skew), Low-Skew (Li-Skew), TGL (Transmission Gate Logic), and DVL, are used to create the one-bit complete adder (Dual Voltage Logic). The amount of switching activity and transistors can be decreased with the suggested design. Combining topologies and selecting the right input signal to transfer change the circuit's power and speed. The Full adder is tested at various voltages using the H-SPICE simulation software. Therefore, the proposed MLS uses 83.53% less power and has a 14.02% Propagation Delay at 0.8 volts.

Author(s) Details:

Chaitanya Kommu,
EECE, GITAM (Deemed to be University), Visakhapatnam, Andhra Pradesh, India.

A. Daisy Rani,
Instrument Technology, Andhra University, Visakhapatnam, Andhra Pradesh, India.

Please see the link here: https://stm.bookpi.org/TIER-V7/article/view/7917