Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate | Chapter 1 | Science and Technology: Developments and Applications Vol. 5

The Large Fan-In and high-performance gates are essential to make portable electronic devices. The efficient realization of high Fan-in XOR gate defines the performance of digital circuits like adders, magnitude comparators etc. In this paper, an efficient realization of three input two-level XOR(Exclusive-OR) is presented. The design of low power and high-speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. The exclusive OR gate is a fundamental building primitive for adders which are mostly used in almost all the arithmetic circuits. Two methods were used to design the proposed XOR, one (i.e. Pass_gate) is purely based on pass transistors with 8 MOSFET and the second method (Modified_Pass_gate) uses transmission gates with 12 transistors. The Modified_Pass_gate offers 86.14% and 6.66% power dissipation reduction compared to static and Pass_gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on a 32 nm technology node (PTM-models) using the Hspice Synopsis simulation tool. From the simulation, it is evident that a definite advantage is in favor of the proposed XOR gate designs. Especially, for the combination, at 0.7v and at 3GHz, the average power

 

Author (s) Details

Chaitanya Kommu
Department of EEC, GITAM University, Visakhapatnam, AP, India.

A Daisy Rani
Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.

 

Please see the book here:- https://doi.org/10.9734/bpi/stda/v5/2365

The Mixed Logic Style based High-performance Binary Adder for ASIC Applications | Chapter 2 | Technological Innovation in Engineering Research Vol. 7

 Binary adders serve as the essential building blocks for developing data processing arithmetic units. In this paper, a novel one-bit complete adder developed using mixed logic design is presented (MLS). Several logic topologies, including High-Skew (Hi-Skew), Low-Skew (Li-Skew), TGL (Transmission Gate Logic), and DVL, are used to create the one-bit complete adder (Dual Voltage Logic). The amount of switching activity and transistors can be decreased with the suggested design. Combining topologies and selecting the right input signal to transfer change the circuit's power and speed. The Full adder is tested at various voltages using the H-SPICE simulation software. Therefore, the proposed MLS uses 83.53% less power and has a 14.02% Propagation Delay at 0.8 volts.

Author(s) Details:

Chaitanya Kommu,
EECE, GITAM (Deemed to be University), Visakhapatnam, Andhra Pradesh, India.

A. Daisy Rani,
Instrument Technology, Andhra University, Visakhapatnam, Andhra Pradesh, India.

Please see the link here: https://stm.bookpi.org/TIER-V7/article/view/7917