Implementation of High Speed 8-bit Multiplier in FPGA with Lesser Adder Elements| Chapter 7 | Novel Perspectives of Engineering Research Vol.7

 This study provides a way for designing an 8-bit multiplication with a shorter delay time and fewer adders. Normally, two numeric data can be multiplied by adding them together again and again. Combinational circuits can be created using the manual multiplication method, which needs binary addition, in the case of binary multiplication. Because the current addition is dependent on the value of the preceding carry, the speed of multiplication is affected by the carry generated by addition. To solve this difficulty, a multiplexer is used to introduce addition, which results in a faster multiplication time. Despite the fact that the proposed design is primarily for FPGA implementation, it may also be implemented in ASIC because the logical latency is reduced when compared to the Xilinx device output.

Author(s) Details:

Dhanabalan,
AAA College of Engineering and Technology, Amathur, Sivakasi, Tamilnadu, India.

Tamil Selvi,
National Engineering College, Kovilpatti, India.

Please see the link here: https://stm.bookpi.org/NPER-V7/article/view/5904