Based on the provided technique for both positive and negative multiplications, this work offers a bit-level systolic design for a matrix-matrix multiplier. To achieve the required performance in many real-time systems and digital image processing applications, highly efficient arithmetic operations are required. One of the most common arithmetic operations in all of these applications is to multiply and accumulate with little processing time. A 4-bit serial-parallel multiplier is provided in this study, which can do both positive and negative multiplications. Except for the last partial product, where all but the last bit is complemented, the Baugh-Wooley algorithm requires complementation of the last bit of each partial product. The suggested approach complements all bits of the final partial product. When compared to the Baugh-Wooley multiplier, this improvement results in a significant reduction in hardware. This multiplier can be used to perform discrete orthogonal transforms, which are commonly utilised in image and signal processing applications. A 2D bit-level systolic architecture for a matrix-matrix multiplier is shown in this research. When compared to similar structures, the proposed structure outperforms them all. When compared to various current constructions, it is concluded that the structure requires less area and time complexity. The suggested systolic architecture is appropriate for VLSI signal processing applications due to its simplicity, regularity, and adaptability.
Author(s) Details:
M. N. Murty,
Department of Physics, NIST, Berhampur-761008, Orissa, India.
S. S. Nayak,
Department of Physics, JITM, Paralakhemundi, Orissa, India.
Binayak Padhy,
Department of Physics, Khallikote (Auto) College, Berhampur-760001, Orissa,
India.
S.N. Panda,
Department of Physics, Gunupur College, Gunupur, Orissa, India.
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