Various Ultrasound Beamformer Designs and Architectures: An Update | Chapter 5 | Theory and Applications of Engineering Research Vol. 7

 A medical ultrasound scanner is a complex digital signal processing system, and it has sophisticated transmitter and receiver signal processing chain. The receive signal processing chain involves many complex signal processing functions, and among them the most complex and significant is the digital beamformer. The beamformer can be considered as the brain of whole signal processing system of the scanner. Beamforming allows message transmission or reception to be directed or spatially selective. It is used in receive signal processing to concentrate the signals of interest in the region of concern as reflections from various tissue structures. As beamformer is the complex signal processing engine in a scanner, practical implementation of the same has significant challenges. This chapter provides an insight of the various receive beamformer architectures implemented in field programmable gate array (FPGA)/application specific integrated circuit (ASIC) for ultrasound imaging.

 

Most of the receive beamformers are implemented using the standard technique delay and sum (DAS). Beamforming in ultrasound instruments for medical imaging has traditionally been implemented using analog delay lines. The concept of dynamic focusing in near field has resulted more complex analog delay structures and were replaced by digital structures. By the availability of high-speed analog to digital converters, and very large-scale integrated circuit (VLSI) technology improvements have now made real time implementation of digital beamformers feasible. The current innovations involve hybrid beamformers utilizing the pros of both analog and digital structures. This chapter discusses the evolution of beamforming architectures from analog to digital environment and the recent trends in beamformer realizations including parallel beamformer implementations. The changes in beamformer designs in order to be compatible to high frequency sensor arrays and yield improved imaging performance, resource optimization, etc. are briefed.

Author(s) Details:

Sreejeesh S. G.,
VLSI Department, National Institute of Electronics and Information Technology, Calicut, India.

Sakthivel R.,
Sense School, Vellore Institute of Technology, Vellore, India.

Jayaraj U. Kidav,
Department of Electronics, National Institute of Electronics and Information Technology, Aurangabad, India.

Please see the link here: https://stm.bookpi.org/TAER-V7/article/view/13684

Improved Hoeffding’s Lemma and Hoeffding’s Tail Bounds: A Recent Study | Chapter 08 | Novel Research Aspects in Mathematical and Computer Science Vol. 3

 This chapter aims to enhance Hoeffding's lemma and, as a result, Hoeffding's tail limits. To begin, we'll offer Hoeffding's lemma with a proof that differs from the original, and then show and prove the better Hoeffding's lemma. The enhancement is for left skewed zero mean random variables X[a,b], with a0 and -a>b. The proof of Hoeffding's improved lemma employs Taylor's expansion, the convexity of exp(sx),sR, and an unnoticed observation made since Hoeffding's publication in 1963 that the maximum of the intermediate function (1-) appearing in Hoeffding's proof is attained at an endpoint rather than at =0.5 as in the case b>-a. We get one-sided and two-sided tail limits for P(Snt) and P(Snt) using Hoeffding's improved lemma. P(Snt) and P(|S n |t), where S n= (i=1)n X i and X i[a i,b i],i=1,...,n are independent zero mean random variables, respectively (not necessarily identically distributed). For any X i:-a ib i,i=1,...,n, we might additionally enhance Hoeffding's two-sided bound. This is because P(-Snt) should raise the one-sided bound, forcing left-skewed intervals to become right-skewed and vice versa.

Author(S) Details

David Hertz
Akko, Israel.

View Book:- https://stm.bookpi.org/NRAMCS-V3/article/view/6815

Study on Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier| Chapter 10 | Novel Perspectives of Engineering Research Vol.7

Based on the provided technique for both positive and negative multiplications, this work offers a bit-level systolic design for a matrix-matrix multiplier. To achieve the required performance in many real-time systems and digital image processing applications, highly efficient arithmetic operations are required. One of the most common arithmetic operations in all of these applications is to multiply and accumulate with little processing time. A 4-bit serial-parallel multiplier is provided in this study, which can do both positive and negative multiplications. Except for the last partial product, where all but the last bit is complemented, the Baugh-Wooley algorithm requires complementation of the last bit of each partial product. The suggested approach complements all bits of the final partial product. When compared to the Baugh-Wooley multiplier, this improvement results in a significant reduction in hardware. This multiplier can be used to perform discrete orthogonal transforms, which are commonly utilised in image and signal processing applications. A 2D bit-level systolic architecture for a matrix-matrix multiplier is shown in this research. When compared to similar structures, the proposed structure outperforms them all. When compared to various current constructions, it is concluded that the structure requires less area and time complexity. The suggested systolic architecture is appropriate for VLSI signal processing applications due to its simplicity, regularity, and adaptability.

Author(s) Details:

M. N. Murty,
Department of Physics, NIST, Berhampur-761008, Orissa, India.

S. S. Nayak,
Department of Physics, JITM, Paralakhemundi, Orissa, India.

Binayak Padhy,
Department of Physics, Khallikote (Auto) College, Berhampur-760001, Orissa, India.

S.N. Panda,
Department of Physics, Gunupur College, Gunupur, Orissa, India.

Please see the link here: https://stm.bookpi.org/NPER-V7/article/view/5907