A medical ultrasound scanner is a complex digital signal processing system, and it has sophisticated transmitter and receiver signal processing chain. The receive signal processing chain involves many complex signal processing functions, and among them the most complex and significant is the digital beamformer. The beamformer can be considered as the brain of whole signal processing system of the scanner. Beamforming allows message transmission or reception to be directed or spatially selective. It is used in receive signal processing to concentrate the signals of interest in the region of concern as reflections from various tissue structures. As beamformer is the complex signal processing engine in a scanner, practical implementation of the same has significant challenges. This chapter provides an insight of the various receive beamformer architectures implemented in field programmable gate array (FPGA)/application specific integrated circuit (ASIC) for ultrasound imaging.
Most of the receive beamformers are implemented using the
standard technique delay and sum (DAS). Beamforming in ultrasound instruments
for medical imaging has traditionally been implemented using analog delay
lines. The concept of dynamic focusing in near field has resulted more complex
analog delay structures and were replaced by digital structures. By the
availability of high-speed analog to digital converters, and very large-scale
integrated circuit (VLSI) technology improvements have now made real time
implementation of digital beamformers feasible. The current innovations involve
hybrid beamformers utilizing the pros of both analog and digital structures.
This chapter discusses the evolution of beamforming architectures from analog
to digital environment and the recent trends in beamformer realizations
including parallel beamformer implementations. The changes in beamformer
designs in order to be compatible to high frequency sensor arrays and yield
improved imaging performance, resource optimization, etc. are briefed.
Author(s) Details:
Sreejeesh S. G.,
VLSI Department, National Institute of Electronics and Information
Technology, Calicut, India.
Sakthivel R.,
Sense
School, Vellore Institute of Technology, Vellore, India.
Jayaraj U. Kidav,
Department of Electronics, National Institute of Electronics and
Information Technology, Aurangabad, India.
Please see the link here: https://stm.bookpi.org/TAER-V7/article/view/13684
