Semiconductor manufacturing at advanced technology nodes
demands inspection systems capable of identifying increasingly subtle,
stochastic, and mixed-type defects. Traditional rule-based and
handcrafted-feature approaches are no longer sufficient to address the
complexity of modern wafer patterns, prompting the integration of artificial
intelligence (AI) into high-volume manufacturing workflows. This chapter
presents a unified framework for AI-driven wafer inspection that combines
convolutional neural networks (CNNs), Vision Transformers (ViTs), and generative
models such as variational autoencoders (VAEs) and generative adversarial
networks (GANs). CNNs are effective for wafer map pattern classification,
learning hierarchical spatial features that capture centre, edge-ring, and
composite wafer failure modes. Transformers extend this capability by modelling
long-range spatial dependencies, enabling improved performance in optical and
SEM imaging scenarios where global context is essential. Generative models
enhance sensitivity to rare or previously unseen defects by learning the
underlying distribution of defect-free patterns and detecting deviations
through reconstruction error or anomaly scoring.
A hybrid ViT–GAN architecture is introduced to demonstrate
how discriminative and generative pathways can be fused to deliver high
accuracy and low false-alarm rates across diverse defect classes. Extensive
comparisons using public datasets and synthetic SEM-like datasets show that AI
models substantially outperform classical techniques, particularly in low-sample
regimes and in the presence of noise, illumination variations, or rotation.
Deployment considerations, including inference speed, model compression, domain
adaptation, and explainability, are discussed to highlight practical challenges
in integrating AI into semiconductor fabs. The chapter concludes with emerging
trends such as self-supervised learning, large vision models, multimodal data
fusion, and temporal defect modelling, which are expected to shape the next
generation of intelligent wafer inspection systems.
Author(s) Details
Balachandar
Jeganathan
ASML, San Jose, CA, USA.
Please see the book here :- https://doi.org/10.9734/bpi/mcsru/v8/6853
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