Showing posts with label semiconductor manufacturing. Show all posts
Showing posts with label semiconductor manufacturing. Show all posts

Thursday, 15 January 2026

AI-Driven Wafer Inspection: Deep Learning, Transformers, and Generative Models for Defect Analysis in Semiconductor Manufacturing | Chapter 10 | Mathematics and Computer Science: Research Updates Vol. 8

 

Semiconductor manufacturing at advanced technology nodes demands inspection systems capable of identifying increasingly subtle, stochastic, and mixed-type defects. Traditional rule-based and handcrafted-feature approaches are no longer sufficient to address the complexity of modern wafer patterns, prompting the integration of artificial intelligence (AI) into high-volume manufacturing workflows. This chapter presents a unified framework for AI-driven wafer inspection that combines convolutional neural networks (CNNs), Vision Transformers (ViTs), and generative models such as variational autoencoders (VAEs) and generative adversarial networks (GANs). CNNs are effective for wafer map pattern classification, learning hierarchical spatial features that capture centre, edge-ring, and composite wafer failure modes. Transformers extend this capability by modelling long-range spatial dependencies, enabling improved performance in optical and SEM imaging scenarios where global context is essential. Generative models enhance sensitivity to rare or previously unseen defects by learning the underlying distribution of defect-free patterns and detecting deviations through reconstruction error or anomaly scoring.

 

 

 

A hybrid ViT–GAN architecture is introduced to demonstrate how discriminative and generative pathways can be fused to deliver high accuracy and low false-alarm rates across diverse defect classes. Extensive comparisons using public datasets and synthetic SEM-like datasets show that AI models substantially outperform classical techniques, particularly in low-sample regimes and in the presence of noise, illumination variations, or rotation. Deployment considerations, including inference speed, model compression, domain adaptation, and explainability, are discussed to highlight practical challenges in integrating AI into semiconductor fabs. The chapter concludes with emerging trends such as self-supervised learning, large vision models, multimodal data fusion, and temporal defect modelling, which are expected to shape the next generation of intelligent wafer inspection systems.

 

 

Author(s) Details

Balachandar Jeganathan
ASML, San Jose, CA, USA.

 

Please see the book here :- https://doi.org/10.9734/bpi/mcsru/v8/6853

 

Saturday, 15 April 2023

Process Optimization of Single-Step Photolithography: An Updated and Novel Approach | Chapter 6 | Fundamental Research and Application of Physical Science Vol. 2

 Thickness control and consistency optimization of the photoresist all the while the photolithography process are thought to be main topics for process engineers to include due to the accuracy and sizing necessities of popular semiconductor devices contemporary. In the Integrated Nanosystems Research Facility at the California Institute for Telecommunications and Information Technology (Calit2), 8 silicon wafers were coated accompanying a positive photoresist chosen Shipley 1827 in a systematic way to boost uniformity and density during alone step photolithography. In this paper, the parameters affecting photoresist width are thoroughly resolved and an economic and novel approach reconstructing uniformity and diameter is presented. First, peeling off is usually observed all along developing processes and it maybe minimized by adding HMDS to advance adhesion. Second, all drain lids are sealed to control the air flow. Finally, ray of light beam check and edge distance measurement are acted to properly position the wafer. The author further discusses various other essential but surely ignored factors that can influence the uniformity and denseness of the photoresist, such as recoating, bubbles, thus. By following this approach, high quality distinct-layer silicon wafer maybe coated calm.

Author(s) Details:

Junyang Zhang,
University of California, Irvine, United States.

Please see the link here: https://stm.bookpi.org/FRAPS-V2/article/view/10149