Recent Study on Power Efficient Arithmetic Circuits for Low Power Applications| Chapter 7 | New Approaches in Engineering Research Vol. 9

 In nanometerscale CMOS technology, integrated circuit design requires low power consumption. According to recent study, applying approximation designs resulted in lower power dissipation when compared to exact designs. In the bulk of multimedia applications, DSP blocks have been used as the core blocks. These DSP blocks implement the majority of video and image processing algorithms, with the ultimate result being an image or video suitable for human viewing. The output of the DSP blocks allows for numerical approximation rather than accuracy because the human sense of observation is limited. As a result of the numerical precision concession, approximation is used.It is possible to suggest an analysis. A rough adder, a rough compressor, and a rough multiplier are proposed in this project. Two approximate adders of type TGA, PA1 and PA2, are proposed and produce improved results, including The PA1 has 14 transistors and two error distances, resulting in a 64.9 percent delay reduction and a 74.33% power decrease, whereas the TGA1 has 16 transistors and greater power consumption. PA2 has two error distances and 20 transistors. PA2, on the other hand, reduces delay by 51.43 percent while reducing power by 67.2 percent. TGA2 contained 22 transistors, whereas PDP had been reduced by 61.97 percent. A 4-2 compressor was recommended in this project to minimise the noise level.the total number of incomplete products On a circuit level, the compressor design required 30 transistors with four mistakes out of 16 possibilities, whereas the current compressor design 1 required 38 transistors and design 2 required 36 transistors. Using the proposed adder and compressors, an approximate 4x4 multiplier is proposed. The proposed multiplier achieves a delay of 124.56 (ns) and a power of 29.332 (uW), which is decreased by 68.01 percent in terms of time and 95.97 percent in terms of power when compared to the exact multiplier.

Author (S) Details

G. Navabharat Reddy
VIT, India.

Dr. P. A. Harsha Vardhini
Department of Electronics and Communication Engineering, Vignan Institute of Technology and Science, India.

Dr. V. Prakasam
PBR VITS, Kavali, India.

Dr. P. Sandeep
Department of Electronics and Communication Engineering, Vignan Institute of Technology and Science, India

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