Design of Low Power Configurable Multiclock Digital System from RTL to GDSII | Chapter 18 | Innovative Solutions: A Systematic Approach towards Sustainable Future

The main duty of the system is to accept orders via a UART receiver, which facilitates various system operations including reading and writing register files and performing ALU-based processing. A 4-byte frame structure is used to convey the results and CRC bits via the UART transmitter communication protocol. A register file and ALU block integration for flexible data manipulation, UART connection for varied command receipt and result transmission, and a multi-clock architecture for efficient operation across several domains are some of the system's important characteristics. The system also prioritizes low- power design concepts to maximize energy efficiency. System definition, architectural design, RTL coding, and adherence to low-power design guidelines are all included in the implementation sequence. The resultant digital system is ready to provide a flexible and economical option for uses that call for.

 

Author (s) Details

 

Veena Sanath Kumar
Dept. of ECE, Acharya Institute of Technology, Bangalore, India.

 

Abhishek L S
Dept. of ECE, Acharya Institute of Technology, Bangalore, India.

 

Chandu H M
Dept. of ECE, Acharya Institute of Technology, Bangalore, India.

 

Chirag A
Dept. of ECE, Acharya Institute of Technology, Bangalore, India.

 

Rohan S
Dept. of ECE, Acharya Institute of Technology, Bangalore, India.

 

 

Please see the book here:- https://doi.org/10.9734/bpi/mono/978-93-49238-47-3/CH18