Design & Optimization of LDMOS Transistor Using Doped Silicon Pockets in Buried Oxide| Chapter 6 | Techniques and Innovation in Engineering Research Vol. 4

 Laterally Diffused MOSFET (LDMOS) devices are attractive devices for the new age flexible electronics applications. LDMOS devices offer various advantages over the conventional MOSFETS without much change in the fabrication flow. The primary force behind LDMOS is its huge volume use, which makes it possible for the technology to be continuously improved. The LDMOS device offers a higher breakdown voltage as compared to the conventional MOSFET devices, a characteristic of interest for the flexible electronics and other applications.

The current research work is aimed at studying the LDMOS device characteristics by way of modelling the device in a process simulator software package and to optimize the device to improve breakdown voltage and reduce the on-resistance. The research work involves a thorough modelling and optimization of the LDMOS device as per the fabrication sequences and studying the various performance metrics.

Author(s) Details:

H. D. Sunitha,
Department of ECE, R. R. Institute of Technology, Bangalore, India.

N. Keshaveni,
Department of ECE, KVGCE, Sullia, Karnataka, India.

Please see the link here: https://stm.bookpi.org/TAIER-V4/article/view/8705

 

Study on Design and Analysis of Ga2O3 Power MOSFETs with Source-field-plated | Chapter 4 | New Approaches in Engineering Research Vol. 16

 This work looks at the design and simulation of Ga2O3 power MOSFETs with source-field plating, as well as the breakdown voltage, interface oxide charges, and their relationship to the threshold voltage. A threshold voltage of -50 V is calculated for the device structure considered. This number is equivalent to reported experimental results with a similar device shape and physical parameters, where a simulation assumes an interface oxide charge density of 5 x1013 /cm2. When a channel doping density of 1.5 x 1016 cm-3 is utilised, simulation results show a breakdown voltage of 600 V and a Ron resistance of 40 mm for Ga2O3 n-MOSFETs. These findings are consistent with other researchers' measurements of electric field breakdown and Ron resistance.

Author(S) Details

H. Fardi
Department of Electrical Engineering, University of Colorado Denver, Colorado, USA.

View Book:- https://stm.bookpi.org/NAER-V16/article/view/4057

Simulation and Design of Vertical Power MOSFETs utilizing Silvaco’s ATLASTM | Chapter 1 | Recent Developments in Engineering Research Vol.5

 

This paper reports on 3C-SiC low-doped drain power MOSFET design and simulation, including key parameters such as the model of avalanche effect ionisation and its relationship to breakdown voltage, the doping dependence of bulk mobility, and the relationship between on-resistance and breakdown voltage. While scaling the parasitic JFET, a number of MOSFETs were built with different blocking layer doping. To mitigate localised breakdown at the p-well / n-type drift layer interface, a stepped doping profile is used. Using a commercially available 2D simulation software, the characteristics of the MOSFETs were obtained. Comparisons made with a 1D analytical model indicate strong agreement between the on-state resistance, current-voltage characteristics, sub-threshold slope and the overall validity of the existing simulation models. As long as there is a proper inclusion of the body impact. Simulation results show that a 600 V, 3C-SiC MOSFET with a thinned substrate, containing a drift layer of 7 ⁇ m and a blocking layer doping density of 1x1016 cm-3, can have an on-state resistance of 0.8 mW-cm2 for the selected material parameters

Author (s) Details

Dr. Hamid Fardi
University of Colorado, Denver Colorado, 1200 Larimer Square, CO 80217-3364, USA.

View Book :- https://bp.bookpi.org/index.php/bpi/catalog/book/273