Design and Analysis of Dynamic Comparator for High Speed Digital Applications | Chapter 7 | Theory and Applications of Engineering Research Vol. 3

Comparators are an essential component in modern digital VLSI design, serving as a fundamental building block. Despite their straightforward logic design, their prevalent use in high-performance systems highlights the criticality of optimizing their performance and power consumption. As a result, there is a constant need to improve the efficiency and effectiveness of comparator designs. A faster and power-efficient comparator is thus desirable. So, here we design a three different comparators with static and dynamic style using CMOS technology and CNTFET technology. The comparator we are designing is a 2-bit magnitude comparator using the PTL design approach. The schematic is designed with the help of Verilog-based netlist file is created which is then simulated in the H-Spice tool to analyze the performance of comparators.

Author(s) Details:

Ch. Ganesh,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

T. Sravan Kumar,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

S. Pallavi,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

G. Sai Preetham Reddy,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

Please see the link here: https://stm.bookpi.org/TAER-V3/article/view/13059