Arbiter is one of the main core elements in the network
scheduler. The significant goal of this work is to design a high-speed and low
execution-time arbiter with lock free and fair arbitration scheme. Arbiter
identifies which type of scheduling scheme can be used by requestors to achieve
an effective resource allocation policy. In this work, four types of arbiters
such as matrix arbiter (MA), ping pong arbiter (PPA), distributive round-robin
arbiter (DRRA) and enhanced ping lock arbiter (EPLA) are designed and analyzed
in terms of area, delay, and speed. MA is worked in square matrix format and
matrix transition is performed for effective routing. The DRRA is designed by
using a multiplexer and counter. Hence, an effective scheduling is carried out
in DRRA. Matrix arbiter provides low delay, but the chip size is large.
Finally, the EPLA requires a lower area than the matrix arbiter and PPA. But
the chip size is more significant than DRRA. Binary tree format is used in PPA.
The PPA provides low chip size and high speed than existing MA and DRRA. The
PPA limits fair arbitration during uniformly distributed active request
patterns. To overcome this problem, PPA is improved with some lock systems to
create an EPLA. A new ping lock arbiter (PLA) leaf and PLA inter structure is
proposed at the gate level to reduce the execution delay, improve the speed and
achieve fair arbitration over all other existing arbiters. Resource allocation,
execution delay, and speed are analyzed using the Xilinx integrated software
environment (ISE) tool. This research work deals with the comparison of
different arbiters where the arbiters are synchronous with the memory access
cycles. In the future, the same work can be incorporated into the logical
circuits where the memory access has more than one clock, which represents the
asynchronous design.
Author(s) Details:
Nagaiyanallur Lakshminarayanan Venkataraman,
Department
of Electronics and Communication Engineering, J.J. College of Engineering and
Technology, Tiruchirapplli, India.
Subramanian
Sumithra,
Department
of Electronics and Communication Engineering, J.J. College of Engineering and
Technology, Tiruchirapplli, India.
Ramaiah Purushothaman,
Department of Electronics and Communication Engineering, J.J.
College of Engineering and Technology, Tiruchirapplli, India.
Subramani Suresh Kumar,
Department of Electronics and Communication Engineering, J.J.
College of Engineering and Technology, Tiruchirapplli, India.
Kathiresan Kokulavani,
Department
of Electronics and Communication Engineering, J.J. College of Engineering and
Technology, Tiruchirapplli, India.
Velankanni
Gowri,
Department
of Electronics and Communication Engineering, J.J. College of Engineering and
Technology, Tiruchirapplli, India.
Please see the link here: https://stm.bookpi.org/TAER-V4/article/view/13098
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