Design and Analysis of Dynamic Comparator for High Speed Digital Applications | Chapter 7 | Theory and Applications of Engineering Research Vol. 3

Comparators are an essential component in modern digital VLSI design, serving as a fundamental building block. Despite their straightforward logic design, their prevalent use in high-performance systems highlights the criticality of optimizing their performance and power consumption. As a result, there is a constant need to improve the efficiency and effectiveness of comparator designs. A faster and power-efficient comparator is thus desirable. So, here we design a three different comparators with static and dynamic style using CMOS technology and CNTFET technology. The comparator we are designing is a 2-bit magnitude comparator using the PTL design approach. The schematic is designed with the help of Verilog-based netlist file is created which is then simulated in the H-Spice tool to analyze the performance of comparators.

Author(s) Details:

Ch. Ganesh,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

T. Sravan Kumar,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

S. Pallavi,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

G. Sai Preetham Reddy,
Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India.

Please see the link here: https://stm.bookpi.org/TAER-V3/article/view/13059

Solitary Electromagnetic Wave Theory and Lossy Line Technologies for Switching Mode Circuit | Book Publisher International

The solitary electromagnetic wave (SEMW) physics theory and the lossy line (LL) technologies in this book have possibility to start a revolution to the industry and academia of digital technologies. At design and analysis of the digital circuit included in the switching mode circuit (SMC), the AC circuit engineering theory that is based on the static electromagnetic physics has been used in current. However, the switching device such as the complemental metal-oxide-semiconductor (CMOS) circuit in the digital circuit is acting quite high speed and in non-periodic and its never static act. Therefore, the accurate design and motion analysis of the digital circuit is impossible by the current method. For such reason, current method of design and analysis of the digital circuit is not accepted by the scientific academia. However, it turns out that this cause is in the scientific field ironically and the theory about the non-periodic electromagnetic wave is not existed in the physics, which engineering should refer to. The digital circuit engineers are facing many types of the difficult problems whenever the development of the equipment and the systems. Among them, EMI including SI (signal integrity) and timing control of the signals are the highly troublesome problems of the digital circuit typically as shown in the first half in detail. SEMW physics theory and LL technologies will solve these problems and will provide easy and highly accurate design and analysis methods. Development process of SEMW physics theory and LL technologies, overview of them, and there few application examples to SMC including the digital circuit and switching mode power supply circuit (SMPC) are presented. The digital circuit consists of switching device and transmission line of power and signal, and SEMW is generated by the switching device. Therefore, the current of the N-channel metal-oxide-semiconductor (N-channel MOS) transistor of CMOS circuit was analyzed in accordance with semiconductor physics. Applying non-linear wave physics and electromagnetic physics to this result, SEMW theory was developed and presented as the hypotheses in electromagnetic physics. When SEMW physics theory is recognized in worldwide, the degree of perfection of the conventional electromagnetic physics will be even higher. According to the SEMW theory, it is estimated that the transmission loss is effective to solve many of above difficult problems facing digital circuit engineers and improve the acting stability of SMC containing the digital circuit. The validation result of the excellent effect of transmission loss at the digital circuit by experiment and calculation are presented. LL technologies will also useful to the circuit on a chip (SoC). It has been believed in the long term that on-chip interconnects must be used the low resistive material based on the AC circuit engineering theory. But according to the SEMW physics theory, it estimates that rather the low conductivity material is suitable for the on-chip interconnects. Therefore, the improvement effect of signal voltage-form and the magnitude of SEMW when any kinds of the low conductivity material are used to the on-chip interconnects was analyzed by the calculation in accordance with the SEMW theory and its result is shown. At last, the design example of the quasi-stationary state closed circuit (QSCC) of the switching power supply circuit by applying the lossy lines and the result of the waveform analysis are shown. I hope you confirm by this example that the signal waveform is improved and the magnitude of SEMW which concerns EMI is reduced.

Author(s) Details:

Hirokazu Tohya,
PhD, CEO President ICAST, Inc.

Please see the link here: https://stm.bookpi.org/SEWTLLTSMC/article/view/11933

Design Procedures of W-Band Low Noise Amplifier for RFIC-5G Applications | Chapter 2 | Research Highlights in Science and Technology Vol. 8

 This phase presents a new approach of the design of a W-band Low Noise Amplifier (LNA) in a  CMOS technology for narrowband and wideband requests. As a part of RFICs, Low Noise Amplifiers (LNA) play a critical role. Being the first block in a recipient, its main trustworthiness is to support enough amplification to counterbalance noise from later blocks (aforementioned the filter and the food processor) while avoiding overloading the blender with excessive gain. The selection of an appropriate portable music player is a fault-finding aspect in crafty an LNA stage that meets the desired accomplishment criteria. Numerous portable music player topologies are available for LNA requests. The proposed LNA employs input equal bandwidth continuations based on the beginning degeneration the earth's features, and it is designed and amended at a center frequency of  and a supply heat of . The obtained results exhibit a cry figure of , a power gain of , and a VSWR of 1.1. The design arrangement for this LNA is based on a together beneficial adjustment between the 30 dB of free gain and the 3 dB of noise figure, that results in strong distance and good bilateral security, as indicated by an recommendation third-order interrupt point of -17 dBm. A detailed accomplishment analysis is bestowed and discussed ahead this paper. With the aim of a complete and strong integration, all lumped pieces and transmission lines are joined on a silicon PCB having ∊_r=11.7 and a dielectric misfortune Tan  for low production costs. The LNA exhibits high time of  at  and demonstrates good cohesion. In future endeavors, reducing capacity consumption will be chased. Consequently, the proposed model holds excellent promise as a suitable choice for 5G-RFIC travelling systems.

Author(s) Details:

Abdelaziz Hamdi,
NOCCS Research Lab., ENISo, ISITCOM, University of Sousse, Tunisia.

Please see the link here: https://stm.bookpi.org/RHST-V8/article/view/11537

Experimenting with Design of Low Power Johnson Counter Using Lector Technique Using 50nm Technology | Chapter 7 | Recent Developments in Engineering Research Vol. 6

 In the design of CMOS VLSI circuits, power dissipation is a significant concern. High power consumption, in the case of battery-powered applications, results in a decrease in battery life and affects the cost of durability, packaging and cooling. The scaling down of the threshold voltage levels in turn induces an exponential increase in sub threshold leakage currents, leading to an increase in leakage power, with technology processes progressing towards deep submicron and nano regimes. A five-fold increase in leakage power dissipation is present as each generation of the manufacturing process progresses. When the circuit is idle, leakage currents flow and so power is lost. For deep submicrons and nanometers, successful leakage power reduction techniques have become important.

Circuit loops. A 4-bit Johnson counter is designed using LECTOR technology in this paper and is analysed with various kinds of sleep techniques. For designing, we have used the digital schematic editor (DSCH); Micro wind Layout Editor is used for simulation and layout generation. In this paper, using various sleep methods and LECTOR techniques, the power consumption of the 4-bit Johnson counter is reduced. Unlike other leakage control techniques, no additional control circuitry is needed by LECTOR to track the circuit states.

Author (s) Details

Dr. A. Yasmine Begum
Department of Electrical and Electronics of Engineering, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, India.

Mr. M. Balaji
Department Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, India.

Dr. N. Padmaja
Department Electronics and Communication Engineering, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, India.

View Book :- https://bp.bookpi.org/index.php/bpi/catalog/book/285

A Comparative Analysis of Two Stage and Folded Cascode Bulk Driven OTA in 0.18um CMOS Process | Chapter 13 | Emerging Trends in Engineering Research and Technology Vol. 7

This paper presence a comparative analysis of two stage and folded cascode bulk driven operational trans conductance amplifier (OTA) topologies for biomedical applications are presented. A two stage bulk driven OTA and Folded cascoded OTA operated with a 1Vpower supply. Bulk-driven PMOStransistors as an input differential opamp provides high input common-mode range (CMR). To achieve low power consumption all transistors must be operated in sub threshold region. The test results are carried out in standard gpdk180nm CMOS technologies.

Author (s) Details

Mr. N. Sharath Babu
Department of Electronics and Communication Engineering, Anurag Group of Institutions, Hyderabad, Telangana, India.

Mr. G. Sreenivasa Raju
Department of Electronics and Communication Engineering, Anurag Group of Institutions, Hyderabad, Telangana, India

Mrs. Amrita Sajja
Department of Electronics and Communication Engineering, Anurag Group of Institutions, Hyderabad, Telangana, India.

View Book :- http://bp.bookpi.org/index.php/bpi/catalog/book/201