Leakage Current Analysis in Mosfets Using Matlab GUI| Chapter 3 | Techniques and Innovation in Engineering Research Vol. 2

 In MOSFETs, leakage current has a mathematical expression. The mathematical expression is inherently complicated. Leakage current is influenced by a variety of factors. This chapter's goal is to examine how various parameters may affect the leakage current. When the input voltage is lower than the threshold voltage, the leakage current occurs. The minimum gate to source voltage necessary to switch on a MOSFET device is known as the threshold voltage. Subthreshold voltage is another name for the leakage current that occurs below the threshold voltage. The gate to source voltage, threshold voltage, drain to source voltage, oxide thickness, channel width, permittivity of the material, temperature, mobility of charge carriers, and subthreshold leakage current all affect it. These parameters are manipulated to see the impact of these parameters is presented through the graph in MATLAB GUI.

Author(s) Details:

Md. Masood Ahmad,
GITAM University, India.

D. Anitha,
GITAM University, India.

Please see the link here: https://stm.bookpi.org/TAIER-V2/article/view/8271

Threshold Voltage and Source to Body Voltage Analysis in Mosfets| Chapter 2 | Techniques and Innovation in Engineering Research Vol. 2

 The lowest voltage necessary to switch on a MOSFET device is known as the threshold voltage. The right body potential can be used to raise or lower the MOSFET threshold voltage. Body bias voltage is another name for the body voltage. This chapter examines several body biassing techniques. The effects of various body bias voltages on the MOSFET device's input and output properties are investigated. The 45nm channel length MOSFETs being investigated. This also goes by the name of 45nm Technology. Devices that use PMOS and NMOS are evaluated for body bias. The active body bias strategy is investigated. To raise the threshold voltage of the PMOS and NMOS devices, reverse body bias is investigated.

Author(s) Details:

Md. Masood Ahmad,
GITAM University, India.

D. Anitha,
GITAM University, India.

Please see the link here: https://stm.bookpi.org/TAIER-V2/article/view/8270

Design and Analysis of Low Power VLSI Full Adders and 32-bit Adders| Book Publisher International

 MOSFET has turned into the most fundamental and central structure block of LSI circuits. In the beyond 40 years, the MOSFET gadgets' scaling expanded execution, diminished size, and high-power utilization. The power utilization is high because of huge spillage flows. Spillage current in nanometer systems is turning into a critical supporter of the all out power dissemination of CMOS circuits. The spillage current in CMOS relies upon edge voltage, channel length, and entryway oxide thickness. Thus, the ID and working of various spillage parts are fundamental for assessing and diminishing spillage power.

Rhythm devices are utilized to confirm the spillage power decrease in snake circuits. The spillage power relies upon spillage current. The spillage current relies upon the subthreshold spillage current. The technique embraced to limit the subthreshold spillage current is through edge voltage increase.

Increase of the edge voltage applied to various full adders, in particular CMOS full snake, Mirror full viper, Transmission door full viper, Manchester full viper, and different full adders as introduced in this proposition. This work planned full adders with 10 MOS transistors,13 MOS semiconductors, and 15 MOS semiconductors. Customary CMOS requires 28 MOS semiconductors to carry out the full viper. The quantity of semiconductors in proposed full adders is under 50% of customary CMOS full viper. The idea of limit increase works for all innovation hubs. This technique has explored different avenues regarding 45nm innovation, and spillage examination in full adders is completed utilizing the Cadence device. Three different full adders are planned and contrasted and existing full adders and planned full adders .32-digit Adders are utilizing different full adders. Spillage examination is done in these 32-bit adders utilizing edge voltage increase. Point of this work is to acquire half decrease in spillage power right away of 32-cycle adders. The general typical spillage power was decreased by 30% in a 32-bit swell convey snake immediately utilizing ten semiconductors full viper. The general typical spillage power was decreased by 27% in a 32-digit convey select viper without changing the general proliferation postpone utilizing ten semiconductors full adders. The general typical spillage power was decreased by 31% in a 32-bit square root convey select viper without changing the general engendering postponement of 32-cycle square root convey select snake utilizing ten semiconductors full viper. The 10-semiconductor full snake has shown the least spillage current out of all the full adders.32-bit viper created utilizing ten semiconductors full viper has low normal spillage power.

Author(s) Details:

Dr. Md. Masood Ahmad,
GITAM University, Hyderabad Campus, India.

Dr. D. Anitha,
GITAM University, Hyderabad Campus, India.

Please see the link here: https://stm.bookpi.org/DALPVLSIFAA/issue/view/781