Design and Development of CPLD Based on Low Power Pipelined 64-bit RISC Processor with Unbiased Floating Point Unit | Chapter 5 | Theory and Applications of Engineering Research Vol. 1

 RISC is a design knowledge where it reduces the complexity of the education set, which will lower the amount of space, time, cost, capacity and heat etc.,. This processor is developed particularly for Arithmetic operations of two together fixed and floating point numbers, arm and logical functions. Pipelining would not flush when branch direction occurs as it is implemented utilizing dynamic arm prediction. This will increase flow in instruction passage and high effective depiction. In RTL coding individual can reduce the dynamic capacity by using clock people present at event technique. In this paper further implement unbiased double precision buoyant point arithmetic operations like adding, subtraction, multiplication and disconnection. The outcome principles of these operations stored in the registers and they can rescue from the same when needed. The reduced power RISC main part of computer with unbiased double accuracy floating point unit is planned without some complication, because the capacity reduction can do ahead end technique. The necessary rule is written in the fittings description language Verilog HDL and it is achieved on Altera MAXV CPLD device. This architecture has enhance indispensable and more important in many applications like signal handle, graphics and medical by utilizing floating point movements.

Author(s) Details:

J. Vijay Kumar,
Faculty of Physics, Sri Krishnadevaraya University College of Engineering & Technology, Anantapur-515 001, Andhra Pradesh, India.

B. Nagaraju,
S. K. University, Anantapur-515 001, Andhra Pradesh, India.

Please see the link here: https://stm.bookpi.org/TAER-V1/article/view/12559

Low Power Sigma Delta Modulator Design | Book Publisher International

 The difficulties faced by integrated circuit designers are caused by fluctuations in process (P), supply voltage (V), and temperature (T), which are complicated by low power design. Process insensitive design approach needs to be adjusted to the circuit/block design in order to take into account PVT changes. Using a process-insensitive design approach, a low-power, temperature-adjusted operational amplifier (Op-Amp) design is covered. The adjusted Op-current Amp's source is made to be more tolerant to process and temperature fluctuations. The suggested Op-performance Amp's is measured against the uncompensated Op-Amp using a variety of performance metrics. When doing Monte-Carlo simulations, the threshold voltage (Vth) variations are taken into account, and the design is improved to produce fewer variations than the uncompensated structures. A low power continuous time sigma delta modulator with an 18 KHz bandwidth and a 64 oversampling ratio (OSR) is created using the proposed compensated Op-Amp. With the suggested compensated Op-Amp, key building components for a sigma delta modulator, such as a difference amplifier and integrator, are constructed. To further reduce power consumption and improve process tolerance, the remaining modulator building components, such as the band gap voltage reference (BGR) circuit and 1-bit SRAM latch, have also been updated. Sigma-delta modulator overall power consumption with these enhanced blocks and compensated Op-Amp is 236 W, compared to 1960 W with uncompensated Op-Amp. As a result, the suggested sigma delta modulator uses less power while providing improved PVT variation tolerance.

Author(s) Details:

Dr. D. Anitha,
Department of ECE, GITAM University, India.

Dr. Md. Masood Ahmad,
Department of ECE, GITAM University, India.

Please see the link here: https://stm.bookpi.org/LPSDMD/issue/view/798

Design and Modelling of Implantable Cardioverter Defibrillator under Low Power High Speed Sub-threshold Operation | Chapter 3 | Technological Innovation in Engineering Research Vol. 5

As a result of significant technical advancements, researchers and scientists have produced designs that work in the subthreshold and near threshold zones. Design experts have recently been more interested in low power circuits as the need for low power consumption devices has increased. The process of subthreshold design has grown more sensitive to PVT changes due to the exponential relationship between current in the subthreshold region, supply voltage (Vgs), and threshold voltage (Vth). Low power electronics have drawn inspiration from subthreshold operation and its underlying principles. This research describes the functionality and performance of a source linked logic circuit's sub threshold design in both static and dynamic modes of operation, and its application as a 28nm implanted cardioverter defibrillator. The study's goals cover SRAM design as well as other techniques, including Schmitt trigger-based SRAM and Source linked SRAM operating in subthreshold designs.

Author (s) Details:

T. Vasudeva Reddy,
ECE Department, B. V. Raju Institute of Technology, Narsapur, Telangana, India.

B. Nareshkumar,
ECE Department, B. V. Raju Institute of Technology, Narsapur, Telangana, India.

R. Anirudh Reddy,
ECE Department, B. V. Raju Institute of Technology, Narsapur, Telangana, India.

P. Kavitha Reddy,
ECE Department, B. V. Raju Institute of Technology, Narsapur, Telangana, India.

Please see the link here: https://stm.bookpi.org/TIER-V5/article/view/7462

A 5V 124MW 64 – Bit Advanced Comparator for DSP Processor | Chapter 8 | Advanced Aspects of Engineering Research Vol. 5

 This study proposes a 5V, 124mw 64-bit Advanced Comparator for DSP Processors. This research compares modified and current 64-bit binary comparator designs to show how they can reduce power consumption and latency. To increase the circuit's performance, some changes were made to the current 64-bit binary comparator architecture. Simulation in Tanner EDA Tool is used to calculate the comparison of updated and existing 64-bit binary comparator designs.

Author(s) Details

Thota Mounika
Department of Electronics and Communication Engineering, Vaagdevi College of Engineering, Warangal, 506005, India.

View Book :- https://stm.bookpi.org/AAER-V5/article/view/988

Frequency Multiplier with Delay Locked Loop -Based Clock Generator for System on Chip Applications | Chapter 11 | Advanced Aspects of Engineering Research Vol. 4

 Any implementation of a particular type of the multiplier in automatic frequency measurement systems is primarily determined by the total allowed variance of both the output frequency and the transducer's input frequency. As a result, in transducers with such a small variance, it is normally better to use frequency multipliers from the first group. The suggested edge combines optimum pace and consistency with an organisational structure and an undetermined overlap. The proposed hybrid digital edge solution offers broadband with low-energy and low-area advantages, as well as being a candidate for low-energy frequency summaries in deep CMOS sub-micrometer. To incorporate the automatic interface, a counter was used instead of a charge pump. Both of the tools for operating stable clock pulses for device on chip applications, as well as the frequency multiplier, are part of the overall system. The frequency multiplication method is carried out with the aid of a clock amplification device based on an edge combiner and C2MOS logic. Finally, a computational analysis is performed to ensure that the output is correct. In comparison to other designs, it is clear that this device consumes less power in the same process.

Author (s) Details

G. Prasanna Kumar
ECE Department, Malla Reddy Engineering College (A), Hyderabad, Telangana, India.

J. Prabhakar
ECE Department, Nalla Malla Reddy Engineering College, Hyderabad, India.

Nagulancha Raju
ECE Department, Vignan Institute of Technology and Science, Hyderabad, Telangana, India.

View Book :- https://stm.bookpi.org/AAER-V4/article/view/644