Analytical Methods for Detecting and Eliminating the Static Hazard in Combinational Logic Circuits | Chapter 1 | Research Updates in Mathematics and Computer Science Vol. 2

 A logic glitch is a kind of unwanted noise, its presence in the output signal can initiate an uncontrollable process, in the next level which is an input signal. There can be distinguished three types of noise that are introduced in (CLC) Combinational Logic Circuits, called hazards (Static, Dynamic and Function Hazards). In this paper, the authors continue the research that consists of a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of POS – Product of Sums, static hazard “0”.

 

In the first method it’s used the consensus theorem to determine the cover term that is equal to the product of the two residual implicants, and in the second method, it’s resolved a Boolean equation system. The authors observed that in the second method, the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.

Author(s) Details:

Mihai Grigore Timis,
Automatic Control and Computer Engineering Faculty, Technical University Gheorghe Asachi Iasi, Romania.

Alexandru Valachi,
Automatic Control and Computer Engineering Faculty, Technical University Gheorghe Asachi Iasi, Romania.

Alexandru Barleanu,
Automatic Control and Computer Engineering Faculty, Technical University Gheorghe Asachi Iasi, Romania.

Andrei Stan,
Automatic Control and Computer Engineering Faculty, Technical University Gheorghe Asachi Iasi, Romania.

Please see the link here: https://stm.bookpi.org/RUMCS-V2/article/view/13940

Synthesis of Digital Logical System by Using Logical Function Decomposition Algorithms implemented with PLD - Programmable Logic Devices | Chapter 7 | Research Updates in Mathematics and Computer Science Vol. 1

 The decomposition problem is old, and well understood when the function to be decomposed is specified by a truth table or has one output only. The paper consists of the use of some logical function decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. We have considered a circuit PAL10L8, which has 10 inputs, 8 outputs and an AND-OR configuration, each NOR having 2 inputs. One important aspect of serial decomposition is the task of selecting ’best candidate’ variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitution results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its "activity" is the number of ’l’s or ’O’s it has in the truth table. If the variable has only ’1’ s or ’0’ s it is the "best candidate" for decomposition, as it is practically redundant. The paper showed that the use of the Boolean function decomposition method reduces the number of circuits necessary for the implementation.

Author(s) Details:

Mihai Grigore Timis,
Automatic Control and Computer Engineering Faculty, Technical University Gh. Asachi, Iasi, Romania.

Alexandru Valachi,
Automatic Control and Computer Engineering Faculty, Technical University Gh. Asachi, Iasi, Romania.

Alexandru Barleanu,
Automatic Control and Computer Engineering Faculty, Technical University Gh. Asachi, Iasi, Romania.

Andrei Stan,
Automatic Control and Computer Engineering Faculty, Technical University Gh. Asachi, Iasi, Romania.

Please see the link here: https://stm.bookpi.org/RUMCS-V1/article/view/13674

Keywords: Combinational circuits, static hazard, logic design, Boolean functions, logical decompositions