Developing digital circuits in today's digital age is constrained by research into various nano devices. The concept of a compact Baugh-Wooley multiplier using reversible logic is discussed in this paper. Despite the fact that there have been several studies on how to construct a reversible multiplier, this is the first in the literature to use the Baugh-Wooley algorithm with reversible logic. A new 5 5 reversible multiplier cell is proposed in this paper, which will be useful in the design of Baugh-Wooley multipliers. The proposed single multiplier cell will add a one-to-one product with the total and carry from the previous cell. This reversible multiplier cell is useful for ensuring array multiplier regularity. The proposed reversible multiplier cell's Toffoli gate synthesis is also given. It is understood that the proposed architecture has fewer gates, constant inputs, and garbage outputs values than current approaches. The circuit can be modified to create n n reversible Baugh-Wooley multipliers.
Author (s) DetailsV. Rajmohan
Department of Electronics and Communication Engineering, College of Engineering, Chennai, India.
O. Uma Maheswari
Department of Electronics and Communication Engineering, College of Engineering, Chennai, India.
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