Showing posts with label APCLRU. Show all posts
Showing posts with label APCLRU. Show all posts

Monday, 3 February 2025

An Evaluation Approach towards Dynamic Memory Balancing in IoT Applications Through Machine Learning Algorithms | Chapter 10 | Science and Technology: Developments and Applications Vol. 4

The term consistent would be more able to coin as the Internet of Things to be the most encouraging innovation which has developed numerous inward branches like the Web of Clinical Things, etc. IoT arranges actuators with comparing propels for giving accommodating information yield. The part of the actuator gadget shifts concerning the application and environment it is sent for. More modest activating machines have a lesser useful cutoff as a result of their limited memory district. Overseeing or keeping up with of capacity of the IoT-based parts is critical for optimizing processing speed and ensuring the responsiveness of selected devices. The composition upholds the Priority Based Memory or Storage Balancing (PBMB) method in the effective treatment of capacity to chip away at the speed of response of the actuator devices. The memory-changing arrangement depends on progressive computer-based intelligence estimation that separates a periodic approach to acting the gadget in managing requests. Considering the assessment, the available memory space is assigned and freed for moving requests and taking care of information. The developing experience is persuaded through time-subordinate transmission direct discernments. The used memory leads procedure works in an adaptable way for evolving time-fundamental and non-surrender tolerant applications by limiting putting away and access delay at the gadget level. The proposed procedure is planned to confine memory abuse, and association delay and to collect the sales taking care of rates.

 

Author (s) Details

S. M. Shamsheer Daula
Department of ECE, G Pulla Reddy Engineering College (A), JNTUA, Kurnool, Andhra Pradesh-518007, India.

 

G. Amjad Khan
Department of ECE, G Pulla Reddy Engineering College (A), JNTUA, Kurnool, Andhra Pradesh-518007, India.

 

G. Ramesh
Department of ECE, G Pulla Reddy Engineering College (A), JNTUA, Kurnool, Andhra Pradesh-518007, India.

 

M. Madhusudhan Reddy
Department of ECE, G Pulla Reddy Engineering College (A), JNTUA, Kurnool, Andhra Pradesh-518007, India.

 

Please see the book here:- https://doi.org/10.9734/bpi/stda/v4/3879 

Monday, 13 July 2020

Adaptive Block Memory Management for Spatial and Temporal Locality in Flash Based Storage Systems: Advanced Study | Chapter 8 | Emerging Trends in Engineering Research and Technology Vol. 7

The shifting of cold clean pages and hot dirty pages along with the inner sets of the cold dirty and the hot clean pages is emphasized in the adaptive predictive clean least recently used technique, but it fails in exploring more on the spatial contents rather than sticking more in the temporal locality maintenance. In that, the concepts of hot page, clean, cold and dirty page management is presented with an efficient kind whose benefits are utilized in the global adaptive algorithm also in both spatial locality and temporal locality management. The role of the three issues in erase, read, write and their interlinks with page transaction from the data buffer cache to the flash translation layer, which is shown in virtual presentation but proves its essence in more nearest way in address mapping, and with the flash storage is implemented using a flash sim simulator version from the very first block padding lru clean first lru or may it be the cold clean first technique. The clear point of growth in each of the sequenced algorithms is simulated at suitable memory sizes showing the prior to latter enhanced may it be in the cluster management or may it be the creation of necessary list like hot list or cold list or key data list. The suggestive solutions have been proved with acceptable solutions and also laid away some more improvable steps to still reduce the speed gaps in the symmetry of the two major issues. The techniques are near to precise in lowering and minimizing the number of times of addressing during the cache handling to efficiency with respect to reducing the erases.

Author(s) Details

 S. M. Shamsheer Daula
G. Pulla Reddy Engineering College (Autonomous), Kurnool – 518007, Andhra Pradesh, India.

View Book :- http://bp.bookpi.org/index.php/bpi/catalog/book/201